Method of measuring threshold voltage of MOS transistor in SRAM array

ABSTRACT

Methods of measuring threshold voltages of MOS transistors in a SRAM array are provided. The SRAM array includes array-arranged cells having a first pass NMOS transistor, a second pass NMOS transistor, a first pull-down NMOS transistor, a second pull-down NMOS transistor, a first pull-up PMOS transistor, and a second pull-up transistor. A cell is selected from the SRAM array by a row decoding and a column decoding. A voltage is applied to a word line, a first bit line, a second bit line, a first power line, a second power line, a first substrate terminal, and/or a second substrate terminal, that are connected to the selected cell. A bit line current of the selected cell is measured to obtain a threshold voltage of a MOS transistor in the selected cell. Threshold voltages of a large number of MOS transistors in a SRAM array can be measured.

CROSS-REFERENCES TO RELATED APPLICATIONS

This application claims priority to Chinese Patent Application No.CN201310425323.0, filed on Sep. 17, 2013, the entire contents of whichare incorporated herein by reference.

FIELD OF THE DISCLOSURE

The present disclosure generally relates to the field of integratedcircuit (IC) technology and, more particularly, relates to methods ofinstant measurement of threshold voltages of MOS transistors in a staticrandom access memory (SRAM) array.

BACKGROUND

As integration level of integrated circuits (ICs) increases and supplyvoltage decreases, dimensions of semiconductor devices of the ICsshrinks. This requires more improvement in chip manufacturing processes.The performance of semiconductor devices is significantly affected byimprovements in chip manufacturing processes. Reliability tests forsemiconductor devices are often conducted to evaluate the performance ofthe semiconductor devices.

Threshold voltage of MOS transistors is an important factor indicatingreliability of memories. Currently, wafer acceptance test (WAT) isusually used to obtain the threshold voltage of a MOS transistor in astorage array of static random access memory (SRAM). The basic principleof WAT is to measure test keys on the scribe lines of a wafer to obtainthe performance parameters of individual semiconductor devices.

As shown in FIG. 1, a wafer 11 is divided into a plurality of chips 13by scribe lines 12. Individual semiconductor devices, which are used astest keys, can be formed on the scribe lines 12 when making the chips13. Referring to FIG. 2, test keys M20 and M21 are located on the scribelines 12. By measuring the test keys M20 and M21, properties of MOStransistors around the scribe line 12 can be obtained.

When measuring threshold voltage of a PMOS transistor in a SRAM storagearray, corresponding DC voltages are applied to bonding pads connectedto drain/source of the test key M20 and the substrate. A sweep voltageis applied to a bonding pad connected to the gate of the test key M20.While applying such sweep voltage, a drain current in the test key M20is measured. A characteristic curve of the measured drain current in thetest key M20 versus the gate voltage (i.e., a difference in potentialbetween the gate and the source) can be obtained, and the thresholdvoltage of the test key M20 can then be calculated according to thecharacteristic curve.

The threshold voltage of the test key M20 represents the thresholdvoltage of the PMOS transistor in the SRAM storage array. Similarly, thethreshold voltage of an NMOS transistor in the SRAM storage array canalso be measured by measuring the threshold voltage of the test key M21.

Accurate assessment of SRAM reliability necessitates a statisticanalysis by obtaining threshold voltages of a large number of MOStransistors in the storage array. However, when using WAT to obtain thethreshold voltages of the MOS transistors, each test key must beconnected to four bonding pads, including bonding pads of the gate,drain, source, and the substrate. Consequently, use of WAT cannot obtainthreshold voltages of a desirably large number of MOS transistors in theSRAM array due to limited space of the scribe line 12 for arranging testkeys and bonding pads.

BRIEF SUMMARY OF THE DISCLOSURE

One aspect of the present disclosure includes a method of measuringthreshold voltages of MOS transistors in a SRAM array. The SRAM arrayincludes array-arranged cells having a first pass NMOS transistor, asecond pass NMOS transistor, a first pull-down NMOS transistor, a secondpull-down NMOS transistor, a first pull-up PMOS transistor, and a secondpull-up transistor. A cell is selected from the SRAM array by a rowdecoding and a column decoding. A voltage is applied to one or more of aword line, a first bit line, a second bit line, a first power line, asecond power line, a first substrate terminal, and a second substrateterminal, that are connected to the selected cell. A bit line current ofthe selected cell is measured to obtain a threshold voltage of a MOStransistor in the selected cell. The MOS transistor in the selected cellincludes the first pass NMOS transistor, the second pass NMOStransistor, the first pull-down NMOS transistor, the second pull-downNMOS transistor, the first pull-up PMOS transistor, or the secondpull-up transistor.

Other aspects of the present disclosure can be understood by thoseskilled in the art in light of the description, the claims, and thedrawings of the present disclosure.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic of a wafer structure;

FIG. 2 is a schematic of scribe lines depicted in FIG. 1;

FIG. 3 is a schematic of a cell structure in a storage array inaccordance with various disclosed embodiments;

FIG. 4 depicts a plot of a drain current versus a gate voltage of afirst pass NMOS transistor in accordance with various disclosedembodiments;

FIG. 5 depicts a plot of a drain current versus a gate voltage of afirst pull-down NMOS transistor in accordance with various disclosedembodiments; and

FIG. 6 depicts a plot of a drain current versus a gate voltage of afirst pull-up PMOS transistor in accordance with various disclosedembodiments.

DETAILED DESCRIPTION

Reference will now be made in detail to exemplary embodiments of thedisclosure, which are illustrated in the accompanying drawings. Whereverpossible, the same reference numbers will be used throughout thedrawings to refer to the same or like parts.

The present disclosure provides methods of measuring threshold voltagesof a large number of MOS transistors in a storage array. The storagearray includes an SRAM storage array. The storage array includes aplurality of storage cells arranged in arrays.

The disclosed methods for measuring threshold voltages of MOStransistors can include, for example, selecting a storage cell from astorage array by row decoding and column decoding; applying voltages toa word line, a first bit line, a second bit line, a first power line, asecond power line, a first substrate, and a second substrate of theselected storage cell; and measuring a bit line current of the selectedcell to obtain a threshold voltage of a MOS transistor in the selectedcell.

For example, when measuring the threshold voltages of the MOStransistors, a storage cell to be measured can be selected. The storagecell to be measured can be selected randomly. For illustration purposes,the storage cell to be measured can be referred to as a target storagecell.

Selection of a target storage cell can include: inputting an addresssignal of the target storage cell through an address line into a rowdecoding circuit and a column decoding circuit of the storage array (orstorage device), e.g., by applying the address signal of the targetstorage cell to a bonding pad connected to the address line, andselecting the target storage cell through decoding by the row decodingcircuit and the column decoding circuit.

When there are N lines of address lines, by row decoding and columndecoding, 2^(N) storage cells can be selected from. A number of Nbonding pads can therefore be placed to measure threshold voltages ofMOS transistors in the 2^(N) storage cells.

As disclosed, since the storage array can be a SRAM storage array, thetarget storage cell can include a plurality of MOS transistors. FIG. 3depicts an exemplary storage cell in accordance with variousembodiments. As shown in FIG. 3, the exemplary storage cell includes afirst pass NMOS transistor PG1, a second pass NMOS transistor PG2, afirst pull-down NMOS transistor PD1, a second pull-down NMOS transistorPD2, a first pull-up PMOS transistor PU1, and a second pull-up PMOStransistor PU2.

A gate electrode of the first pass NMOS transistor PG1 can be connectedto a gate electrode of the second pass NMOS transistor PG2 and thenfurther connected to a word line WL. A first electrode of the first passNMOS transistor PG1 can be connected to a first bit line BL. A secondelectrode of the first pass NMOS transistor PG1 can be connected to afirst electrode of the first pull-up PMOS transistor PU1, a firstelectrode of the first pull-down NMOS transistor PD1, a gate electrodeof the second pull-up PMOS transistor PU2, and a gate electrode of thesecond pull-down NMOS transistor PD2.

A first electrode of the second pass NMOS transistor PG2 can beconnected to a second bit line BB. A second electrode of the second passNMOS transistor PG2 can be connected to a first electrode of the secondpull-up PMOS transistor PU2, a first electrode of the second pull-downNMOS transistor PD2, a gate electrode of the first pull-up PMOStransistor PU1, and a gate electrode of the first pull-down NMOStransistor PD1.

A second electrode of the first pull-up PMOS transistor PU1 can beconnected to a second electrode of the second pull-up PMOS transistorPU2 and further be connected to a first supply line Vdd. A secondelectrode of the first pull-down NMOS transistor PD1 can be connected toa second electrode of the second pull-down NMOS transistor PD2 andfurther be connected to a second supply line Vss.

Substrates of the first pull-up PMOS transistor PU1 and the secondpull-up PMOS PU2 can be connected together to form a first substrateterminal NW. Substrates of the first pass NMOS transistor PG1, thesecond pass NMOS transistor PG2, the first pull-down NMOS transistorPD1, and the second pull-down NMOS transistor PD2 can be connectedtogether to become a second substrate terminal PW.

When the storage cell shown in FIG. 3 is a target storage cell selectedby a row decoding and a column decoding, different test voltages can beapplied to measure threshold voltages of different MOS transistors inthe target storage cell.

For illustration purposes, the disclosed methods are described hereinusing the method for measuring a threshold voltage of the first passNMOS transistor PG1 as an example.

When measuring a threshold voltage of the first pass NMOS transistorPG1, the gate electrodes of both the second pull-down NMOS transistorPD2 and the first pull-down NMOS transistor PD1 are first initialized.For example, the gate electrode of the second pull-down NMOS transistorPD2 (i.e., the second electrode of the first pass NMOS transistor PG1)is initialized to be at low level, and the gate electrode of the firstpull-down NMOS transistor PD1 (i.e., the second electrode of the secondpass NMOS transistor PG2) is initialized to be at high level.

Specifically, after applying a supply voltage of the storage array tothe storage array (i.e., after powering on the storage array), a highlevel voltage can be applied to the word line WL to switch on (conduct)both the first pass NMOS transistor PG1 and the second pass NMOStransistor PG2. Using a write control circuit, a low level voltage isapplied to the first bit line BL, and a high level voltage is applied tothe second bit line BB.

The low level voltage applied to the first bit line BL transmits throughthe first pass NMOS transistor PG1 to the gate electrode of the secondpull-down NMOS transistor PD2 to cut off the second pull-down NMOStransistor PD2. The high level voltage applied to the second bit line BBtransmits through the second pass NMOS transistor PG2 to the gateelectrode of the first pull-down NMOS transistor PD1 to switch on(conduct) the first pull-down NMOS transistor PD1. The initializationprocess is then completed.

After initializing the gate electrodes of the second pull-down NMOStransistor PD2 and the first pull-down NMOS transistor PD1, the supplyvoltage of the storage array can be applied to the first power line Vdd,the first substrate terminal NW, the first bit line BL, and the secondbit line BB. A zero voltage can be applied to the second power line Vssand the second substrate terminal PW. Voltage of the word line WL cansweep in a pre-set step voltage from 0 V to the supply voltage of thestorage array.

During the voltage sweeping of the word line WL, the voltages applied tothe first power line Vdd, the first substrate terminal NW, the first hitline BL, the second bit line BB, the second power line Vss, and thesecond substrate terminal PW are kept unchanged to cut off the firstpull-up PMOS transistor PU1, the second pull-up PMOS transistor PU2, andthe second pull-down NMOS transistor PD2.

After initialization, a second electrode of the first pass NMOStransistor PG1 is at a low level, and a second electrode of the secondpass NMOS transistor PG2 is at a high level. As such, during the voltagesweeping of the word line WL, the first pull-down NMOS transistor PD1 isalways “on” to electrically connect the second electrode of the firstpass NMOS PG1 with the second power line Vss.

The voltage of the work line WL is the gate voltage of the first passNMOS transistor PG1. The voltage of the first bit line BL is the drainvoltage of the first pass NMOS transistor PG1. The voltage of the secondpower line Vss is the source voltage of the first pass NMOS transistorPG1.

The voltage applied to the word line WL increases gradually from 0 V, bya pre-set step voltage, to the supply voltage of the storage array.Accordingly, the voltage difference (i.e., the gate-source voltage)between the gate electrode and the source electrode of the first passNMOS transistor PG1 keeps increasing to switch on the first pass NMOStransistor PG from an “off” state.

The supply voltage of the storage array can range from about 0.5 V toabout 2.5V. The pre-set step voltage can range from about 0.005 V toabout 0.1 V. In an exemplary embodiment, the supply voltage of thestorage array can be about 1 V and the pre-set step voltage can be about0.02V.

A drain current of the first pass NMOS transistor PG1 (i.e., a currentof the first bit line BL) can be measured while the voltage of the wordline WL sweeping from 0 V to the supply voltage of the storage array.For example, a corresponding current of the first bit line BL can bemeasured each time when the voltage of the word line increases, whichcan be collected either directly using power monitor unit (PMU) or anyother suitable devices without limitations.

After drain current data of the first pass NMOS transistor PG1 arecollected at different gate-source voltages, a characteristic curve ofdrain current versus gate-source voltage of the first pass NMOStransistor PG1 can be obtained.

FIG. 4 shows a graph of drain current versus gate-source voltage of thefirst pass NMOS transistor PG1. In FIG. 4, abscissa having a unit of mVrepresents the gate-source voltage of the first pass NMOS transistorPG1. Ordinate having a unit of nA represents the drain current of thefirst pass NMOS transistor PG1. A series of discrete data points can bedrawn in FIG. 4 based on the voltages applied to the word line WL andthe measured corresponding drain currents of the first pass NMOStransistor PG1. A solid line in FIG. 4 can be obtained by connecting thediscrete data points successively. The solid line represents acharacteristic curve of drain current versus gate-source voltage of thefirst pass NMOS transistor PG1.

According to the characteristic curve of the drain current versusgate-source voltage of the first pass NMOS transistor PG1, a thresholdvoltage of the first pass NMOS transistor PG1 can then be calculatedusing any suitable approaches without limitations. In an exemplaryembodiment, a constant current coefficient method can be used tocalculate the threshold voltage of the first NMOS transistor PG1.

First, a constant current Icc of the first pass NMOS transistor PG1 iscalculated: Icc=100nA×W/L, where W and L are the width and the length ofthe first pass NMOS transistor PG1, respectively. After obtaining theconstant current Icc, a data point with an ordinate value being equal tothe constant current Icc of the first pass NMOS transistor PG1 is thenlocated on the characteristic curve of drain current versus gate-sourcevoltage of the first pass NMOS transistor PG1, and the abscissa value ofthe data point is taken as the threshold voltage of the first pass NMOStransistor PG1.

Measurements of threshold voltages of MOS transistors provided by thisdisclosure are performed for a storage cell. A simulation test isconducted for an individual MOS transistor to verify the thresholdvoltage measured in an exemplary embodiment.

When conducting a simulation test for an individual MOS transistor, thesupply voltage of the storage array is applied to a first electrode ofthe individual MOS transistor, and a zero voltage is applied to a secondelectrode of the individual MOS transistor. The gate voltage of theindividual MOS transistor can sweep from 0 V to the supply voltage ofthe storage array by a pre-set step voltage, and a drain current (e.g.,a current of the first electrode of the individual MOS transistor) ofthe individual MOS transistor is collected during the voltage sweeping.

The supply voltage of the storage array and the pre-set step voltage arethe same as corresponding voltages for testing the first pass NMOStransistor PG1, such that the applied voltage for testing a thresholdvoltage of the individual MOS transistor is the same as the appliedvoltage for testing a threshold voltage of the first pass NMOStransistor PG1.

A characteristic curve of drain current versus gate-source voltage ofthe individual MOS transistor is shown as the dashed line in FIG. 4. Asshown in FIG. 4, the solid line and the dashed line are almost orsubstantially overlapped, e.g., by little differences. In addition,differences between the solid line and the dashed line occur at where adrain current is relatively high, which shows that the differences occurprimarily after the MOS transistor is switched on. The differences havelittle or no effect on the threshold voltage of the MOS transistor. Assuch, the threshold voltage of the first pass NMOS transistor PG1measured in this exemplary embodiment is verified to be accurate.

Measurement of a threshold voltage of the second pass NMOS transistorPG2 is disclosed herein. The threshold voltage of the second pass NMOStransistor PG2 can be measured using a similar approach as that formeasuring the threshold voltage of the first pass NMOS transistor PG1but with some distinctions as described as follows. When initializingthe gate electrodes of both the second pull-down NMOS transistor PD2 andthe first pull-down NMOS transistor PD1, the gate electrode of thesecond pull-down NMOS transistor PD2 (i.e., a second electrode of thefirst pass NMOS transistor PG1) is initialized to be at a high level,and the gate electrode of the first pull-down NMOS transistor PD1 (i.e.,a second electrode of the second pass NMOS transistor PG2) isinitialized to be at a low level. A drain current of the second passNMOS transistor PG2 can then be obtained by measuring a current of thesecond bit line BB.

Specifically, after applying a supply voltage to the storage array, ahigh level voltage is applied to the word line WL to switch on both thefirst pass NMOS transistor PG1 and the second pass NMOS transistor PG2.A high level voltage and a low level voltage are applied through a writecontrol circuit to the first bit line BL and the second bit line BB,respectively.

The high level voltage applied to the first bit line BL transmitsthrough the first pass NMOS transistor PG1 to the gate electrode of thesecond pull-down NMOS transistor PD2 to switch on the second pull-downNMOS transistor PD2. The low level voltage applied to the second bitline BB transmits through the second pass NMOS transistor PG2 to thegate electrode of the first pull-down NMOS transistor PD1 to cut off thefirst pull-down NMOS transistor PD1. Initialization process is thencompleted.

After initializing the gate electrodes of the second pull-down NMOStransistor PD2 and the first pull-down NMOS transistor PD1, the supplyvoltage of the storage array can be applied to the first power line Vdd,the first substrate terminal NW, the first bit line BL, and the secondbit line BB. A zero voltage can be applied to the second power line Vssand the second substrate terminal PW. Voltage of the word line WL cansweep by a pre-set step voltage from 0 V to the supply voltage of thestorage array.

In an exemplary embodiment, the supply voltage of the storage array andthe pre-set step voltage can be the same as the corresponding voltagesin the aforementioned embodiment for measurement of the thresholdvoltage of the first pass NMOS transistor PG1.

A drain current of the second pass NMOS transistor PG2 (i.e., a currentof the second bit line BB) can be measured while the voltage of the wordline WL sweeping from 0 V to the supply voltage of the storage array.After the drain current data of the second pass NMOS transistor PG2 arecollected at different gate-source voltages of the second pass NMOStransistor PG2, a characteristic curve of drain current versusgate-source voltage of the second pass NMOS transistor PG2 can beobtained. A threshold voltage of the second pass NMOS transistor PG2 canthen be calculated based on the characteristic using a constant currentcoefficient method.

Measurement of a threshold voltage of the first pull-down NMOStransistor PD1 is disclosed herein. When measuring a threshold voltageof the first pull-down NMOS transistor PD1, no initialization need to beconducted for the gate electrodes of both the second pull-down NMOStransistor PD2 and the first pull-down NMOS transistor PD1. Afterselecting a target storage cell, the supply voltage of the storage arraycan be applied to the second power line Vss and the first substrateterminal NW. A zero voltage can be applied to the first bit line BL andthe second substrate terminal PW. A control voltage can be applied tothe word line WL. The voltages of the second bit line BB and the firstpower line Vdd can sweep from 0 V to the supply voltage of the storagearray by a pre-set step voltage.

The supply voltage of the storage array and the pre-set step voltage arethe same as the corresponding voltages in the exemplary embodiment formeasuring the threshold voltage of the first pass NMOS transistor (i.e.,the supply voltage of the storage array is about 1 V and the pre-setstep voltage is about 0.02V). The control voltage is higher than thesupply voltage of the storage array, such that the second pass NMOStransistor PG2 can stay at an “on” state when the voltage of the secondbit line BB reaches the supply voltage of the storage array. The controlvoltage can range from about 1V to about 3V. In an exemplary embodiment,the control voltage is about 1.5V.

During the voltage sweeping of the second bit line BB, the voltagesapplied to the first power line Vdd, the first substrate terminal NW,the first bit line BL, the word line WL, the second power line Vss, andthe second substrate terminal PW are all kept unchanged to cut off thefirst pull-up PMOS transistor PU1, the second pull-up PMOS transistorPU2, and the second pull-down NMOS transistor PD2.

Since the control voltage applied to the word line WL is higher than thesupply voltage of the storage array, both the first pass NMOS transistorPG1 and the second pass NMOS transistor PG2 can stay at an “on” stateall the time during the voltage sweeping of the second bit line BB. Assuch, a first electrode of the first pull-down NMOS transistor PD1 canbe connected with the first bit line BL, and the gate electrode of thefirst pull-down NMOS transistor PD1 can be connected with the second bitline BB.

The gate voltage of the first pull-down NMOS transistor PD1 is thevoltage of the second bit line BB; the source voltage of the firstpull-down NMOS transistor PD1 is the voltage of the first bit line BL;and the drain voltage of the first pull-down NMOS transistor PD1 is thevoltage of the second power line Vss.

The voltage applied to the second bit line BB can increase graduallyfrom 0V. Each increased voltage is a pre-set step voltage until thesupply voltage of the storage array is reached. Hence, voltagedifference (i.e., a gate-source voltage) between the gate electrode andthe drain electrode of the first pull-down NMOS transistor PD1 can keepincreasing to switch on the first pull-down NMOS transistor PD1 from an“off” state.

A drain current of the first pull-down NMOS transistor PD1 (i.e., acurrent of the first bit line BL) can be measured while the voltage ofthe second bit line BB sweeping from 0 V to the supply voltage of thestorage array. Specifically, a corresponding current of the first bitline BL can be measured each time when the voltage of the second bitline increases, which can be measured using any suitable methods withoutlimitations (e.g., referring to the exemplary embodiment for measuring athreshold voltage of the first pass NMOS transistor PG1 as discussedabove).

FIG. 5 depicts a graph of drain current versus gate-source voltage ofthe first pull-down NMOS transistor PD1. The solid line in FIG. 5represents a characteristic curve of drain current versus gate-sourcevoltage of the first pill-down NMOS transistor PD1. A threshold voltageof the first pull-down NMOS transistor PD1 can then be calculated basedon the characteristic curve of drain current versus gate-source voltageof the first pull-down NMOS transistor PD1 (e.g., referring to theexemplary embodiment for measuring a threshold voltage of the first passNMOS transistor PG1).

As depicted in the exemplary embodiment for measuring a thresholdvoltage of the first pass NMOS transistor PG1, a simulation test isconducted in this exemplary embodiment for an individual MOS transistor.When conducting a simulation test of an individual MOS transistor, thesupply voltage of the storage array is applied to a first electrode ofthe individual MOS transistor, and a zero voltage is applied to a secondelectrode of the individual MOS transistor. The gate voltage of theindividual MOS transistor can sweep from 0 V to the supply voltage ofthe storage array by a pre-set step voltage, and a drain current (i.e.,a current of the first electrode of the individual MOS transistor) ofthe individual MOS transistor is collected during the voltage sweeping.

The supply voltage of the storage array and the pre-set step voltage arethe same as the corresponding voltages for testing a threshold voltageof the first pull-down NMOS transistor PD1, such that the appliedvoltage for testing a threshold voltage of the individual MOS transistoris the same as the applied voltage for testing a threshold voltage ofthe first pull-down NMOS transistor PD1.

The dashed line in FIG. 5 represents a characteristic curve of draincurrent versus gate-source voltage of the individual MOS transistor. Asshown in FIG. 5, the solid line and the dashed line are almost orsubstantially overlapped, e.g., with little differences. In addition,the differences between the solid line and the dashed line occur atwhere the drain current is relatively high, which shows that thedifferences occur primarily after the MOS transistor is switched on. Thedifferences have a little or no effect on a threshold voltage of the MOStransistor. As such, the threshold voltage of the first pull-down NMOStransistor PD1 measured in this exemplary embodiment is verified to beaccurate.

Disclosed herein is an exemplary embodiment for measuring a thresholdvoltage of the second pull-down NMOS PD2. A threshold voltage of thesecond pull-down NMOS transistor PD2 can be measured using a similarapproach as that for measuring a threshold voltage of the firstpull-down NMOS transistor PD, but with some distinctions as described asfollows. The voltages applied to the first bit line BL and the secondbit line BB are opposite to the corresponding voltages applied to thefirst bit line BL and the second bit line BB in the exemplary embodimentfor measuring the threshold voltage of the first pull-down NMOStransistor PD1. A drain current of the second pull-down NMOS transistorPD2 can be obtained by measuring a current of the second bit line BB.

Specifically, after selecting a target storage cell, the supply voltageof the storage array can be applied to the second power line Vss and thefirst substrate terminal NW. A zero voltage can be applied to the secondbit line BB and the second substrate terminal PW. A control voltage canbe applied to the word line WL. The voltages of the first bit line BLand the first power line Vdd can sweep from 0 V to the supply voltage ofthe storage array by a pre-set step voltage. The control voltage, thesupply voltage of the storage array, and the pre-set step voltage canrefer to the exemplary embodiment for measuring a threshold voltage ofthe first pull-down NMOS transistor PD1

A drain current of the second pull-down NMOS transistor PD2 (i.e., acurrent of the second bit line BB) can be measured while the voltage ofthe first bit line BL sweeping from 0 V to the supply voltage of thestorage array. Once drain current data of the second pull-down NMOStransistor PD2 are collected at various gate-source voltages, acharacteristic curve of drain current versus gate-source voltage of thesecond pull-down NMOS transistor PD2 can be plotted. A constant currentcoefficient method can be used to obtain a threshold voltage of thesecond pull-down NMOS transistor PD2.

Disclosed herein is an exemplary embodiment for measuring a thresholdvoltage of the first pull-up PMOS transistor PU1. When measuring athreshold voltage of the first pull-up PMOS transistor PU1, noinitialization need to be conducted for the gate electrodes of both thesecond pull-down NMOS transistor PD2 and the first pull-down NMOStransistor PD1. After selection of a target storage cell, the supplyvoltage of the storage array can be applied to the first bit line BL andthe first substrate terminal NW; a zero voltage can be applied to thefirst power line Vdd and the second substrate terminal PW; and a controlvoltage can be applied to the word line WL. The voltages of the secondbit line BB and the second power line Vss can sweep from the supplyvoltage of the storage array to 0V by a pre-set step voltage.

The supply voltage of the storage array and the pre-set step voltage arethe same as the corresponding voltages in the exemplary embodiment formeasuring a threshold voltage of the first pass NMOS transistor (i.e.,the supply voltage of the storage array is about 1 V and the pre-setstep voltage is about 0.02V). The control voltage is higher than thesupply voltage of the storage array, such that the second pass NMOStransistor PG2 can stay at an “on” state when the voltage of the secondbit line BB reaches the supply voltage of the storage array. The controlvoltage can range from about 1V to about 3V. In this exemplaryembodiment, the control voltage can be the same as the control voltageapplied in the exemplary embodiment for measuring a threshold voltage ofthe first pull-down NMOS transistor PD1 (i.e., about 1.5V).

During the voltage sweeping of the second bit line BB, the voltagesapplied to the first power line Vdd, the first substrate terminal NW,the first bit line BL, the word line WL, the second power line Vss, andthe second substrate terminal PW are all kept unchanged to cut off thefirst pull-down NMOS transistor PD1, the second pull-up PMOS transistorPU2, and the second pull-down NMOS transistor PD2.

Since the control voltage applied to the word line WL is higher than thesupply voltage of the storage array, both the first pass NMOS transistorPG1 and the second pass NMOS transistor PG2 can stay at an “on” stateall the time during the voltage sweeping of the second bit line BB. Assuch, a first electrode of the first pull-up PMOS transistor PU1 can beconnected with the first bit line BL, and the gate electrode of thefirst pull-up PMOS transistor PU1 can be connected with the second bitline BB.

The gate voltage of the first pull-up PMOS transistor PU1 is the voltageof the second bit line BB; the drain voltage of the first pull-up PMOStransistor PU1 is the voltage of the first bit line BL; and the sourcevoltage of the first pull-up PMOS transistor PU1 is the voltage of thefirst power line Vdd.

The voltage applied to the second bit line BB can decrease graduallyfrom the supply voltage of the storage array. Each decreased voltage isthe pre-set step voltage until a zero voltage is reached. Hence, thevoltage difference (i.e., the gate-source voltage) between the gateelectrode and the source electrode of the first pull-up PMOS transistorPU1 can keep increasing to switch on the first pull-up PMOS transistorPU1 from an “off” state.

A drain current of the first pull-up PMOS transistor PU1 (i.e., acurrent of the first bit line BL) can be measured while the voltage ofthe second bit line BB sweeping from the supply voltage of the storagearray to the zero voltage. Specifically, a corresponding current of thefirst bit line BL can be measured each time when the voltage of thesecond bit line BB decreases, which can be collected using any suitablemethods without limitations (e.g., referring to the exemplary embodimentfor measuring a threshold voltage of the first pass NMOS transistorPG1).

FIG. 6 depicts a graph of drain current versus gate-source voltage ofthe first pull-up PMOS transistor PU1. The solid line in FIG. 6represents a characteristic curve of drain current versus gate-sourcevoltage of the first pull-up PMOS transistor PU1. The threshold voltageof the first pull-up PMOS transistor PU1 can then be calculated based onthe characteristic curve of drain current versus gate-source voltage ofthe first pull-up PMOS transistor PU1 (e.g., referring to the exemplaryembodiment for measuring a threshold voltage of the first pass NMOStransistor PG1).

As depicted in the exemplary embodiment for measuring a thresholdvoltage of the first pass NMOS transistor PG1, a simulation test isconducted in this exemplary embodiment for an individual MOS transistor.When conducting a simulation test of an individual MOS transistor, thesupply voltage of the storage array is applied to a first electrode ofthe individual MOS transistor, and a zero voltage is applied to a secondelectrode of the individual MOS transistor. The gate voltage of theindividual MOS transistor can sweep from the supply voltage of thestorage array to the zero voltage in a pre-set step voltage. A draincurrent (i.e., a current of the first electrode of the individual MOStransistor) of the individual MOS transistor is collected during thevoltage sweeping.

The supply voltage of the storage array and the pre-set step voltage arethe same as the corresponding voltages for testing a threshold voltageof the first pull-up PMOS transistor PU1, such that the applied voltagefor testing a threshold voltage of the individual MOS transistor is thesame as the applied voltage for testing a threshold voltage of the firstpull-up PMOS transistor PU1.

The dashed line in FIG. 6 depicts a characteristic curve of draincurrent versus gate-source voltage of the individual MOS transistor. Asshown in FIG. 6, the solid line and the dashed line are almost orsubstantially overlapped, e.g., with little differences. In addition,differences between the solid line and the dashed line occur at wherethe drain current is relatively high, which shows that the differencesoccur primarily after the MOS transistor is switched on. The differenceshave a little or no effect on the threshold voltage of the MOStransistor. As such, the threshold voltage of the first pull-up PMOStransistor PU1 measured in this exemplary embodiment is verified to beaccurate.

Disclosed herein is an exemplary embodiment for measuring a thresholdvoltage of the second pull-up PMOS transistor PU2. A threshold voltageof the second pull-up PMOS transistor PU2 can be measured using asimilar approach as that for measuring a threshold voltage of the firstpull-up PMOS transistor PU1, but with some distinctions as described asfollows. For the second pull-up PMOS transistor PU2, the voltagesapplied to the first bit line BL and the second bit line BB can beopposite to corresponding voltages applied in the exemplary embodimentfor measuring a threshold voltage of the first pull-up PMOS transistorPU1; and a drain current of the second pull-up PMOS transistor PU2 canbe obtained by measuring a current of the second bit line BB.

Specifically, after selection of a target storage cell, the supplyvoltage of the storage array can be applied to the second bit line BBand the first substrate terminal NW; a zero voltage can be applied tothe first power line Vdd and the second substrate terminal PW; and acontrol voltage can be applied to the word line WL. The voltages of thefirst bit line BL and the second power line Vss can sweep from thesupply voltage of the storage array to 0V by a pre-set step voltage. Thecontrol voltage, the supply voltage of the SRAM array, and the pre-setstep voltage can be referred to the exemplary embodiment for measuring athreshold voltage of the first pull-down NMOS transistor PD1.

A drain current of the second pull-up PMOS transistor PU2 (i.e., acurrent of the second bit line BB) can be measured while the voltage ofthe first bit line BL sweeping from the supply voltage of the storagearray to the zero voltage. Once drain current data of the second pull-upPMOS transistor PU2 can be collected at various gate-source voltages, acharacteristic curve of drain current versus gate-source voltage of thesecond pull-up PMOS transistor PU2 can be plotted. A constant currentcoefficient method can be used to calculate the threshold voltage of thesecond pull-up PMOS transistor PU2.

In this manner, the disclosure provides methods of measuring a thresholdvoltage of a MOS transistor, e.g., by directly measuring thresholdvoltages of MOS transistors in a storage array, without positioning testkeys on the scribe lines of a wafer. Only bonding pads connected to theword line, the first bit line, the second bit line, the first powerline, the second power line, the first substrate, the second substrate,and address lines of the storage array are need to be placed on thescribe lines of the wafer. Further, when the address line connects to anumber of N bonding pads, 2^(N) storage cells in the storage array canbe selected for measurement by a row decoding and a column decoding tocollect threshold voltages of about a number of 6×2^(N) MOS transistors.Methods disclosed for measuring threshold voltages of MOS transistors ina storage array can measure a large number of MOS transistors in thestorage array.

Table. 1 illustrates threshold voltages of MOS transistors of ten failedstorage cells measured in accordance with various disclosed embodiments.The ten failed storage cells are labeled as cells 1-10. The failedthreshold voltages are identified, as shown in Table 1.

TABLE 2

To evaluate measurement accuracy of methods provided by the disclosure,a nanoprobe method with a high accuracy is employed to measure thefailed storage cell 9. Table 2 illustrates a threshold voltage of a MOStransistor of the failed storage cell 9 in Table 1 measured by thenanoprobe method, which shows a high agreement between the thresholdvoltage of the MOS transistor measured by the disclosed methods and thethreshold voltage of the same MOS transistor measured by the nanoprobemethod. The nanoprobe method has high measurement accuracy for measuringa threshold voltage of a MOS transistor. However, the nanoprobe methodhas a slow measurement rate with a high cost, and needs to exposeelectrodes of a MOS transistor prior to measurement. The nanoprobemethod can also damage a wafer. In contrast, methods provided by thepresent disclosure have a fast measurement rate with a low cost, and donot require electrodes of a MOS transistor to be exposed prior tomeasurement. Also methods disclosed herein do not damage a wafer.

TABLE 1

In this manner, threshold voltages of other MOS transistors in the SRAMarray can be obtained (e.g., the second pass NMOS transistor, the firstpull-down NMOS transistor, the second pull-down NMOS transistor, thefirst PMOS transistor, and the second pull-up PMOS transistor). Thepre-set step voltage can range from about 0.005 V to about 0.1 V. Thesupply voltage of the SRAM array can range from about 0.5 V to about 2.5V. The control voltage can range from about 1 V to about 3 V.

Advantages of the disclosure over conventional measurements can includea direct measurement of threshold voltages of MOS transistors in theSRAM array without positioning test keys on the scribe line of wafer.Only bonding pads connecting to the word line, the first bit line, thesecond bit line, the first power line, the second power line, the firstsubstrate, the second substrate, and the address line of the SRAM arrayare required to be placed on the scribe line. Further, when the addressline connects to a number of N pads, about 2^(N) cells in the SRAM arraycan be selected for measurement through row decoding and column decodingto collect a large number of threshold voltages of MOS transistors inthe SRAM array. Additionally, the disclosed measurement method providesno exposure of MOS transistor terminals, no damage to the wafer, and isa fast and low-cost method for threshold voltage measurement of MOStransistors.

Other applications, advantages, alternations, modifications, orequivalents to the disclosed embodiments are obvious to those skilled inthe art.

What is claimed is:
 1. A method of measuring threshold voltages of MOStransistors in a SRAM array, comprising: providing the SRAM arrayincluding array-arranged cells each including a first pass NMOStransistor, a second pass NMOS transistor, a first pull-down NMOStransistor, a second pull-down NMOS transistor, a first pull-up PMOStransistor, and a second pull-up transistor; selecting a cell from theSRAM array by a row decoding and a column decoding; applying a voltageto one or more of a word line, a first bit line, a second bit line, afirst power line, a second power line, a first substrate terminal, and asecond substrate terminal, that are connected to the selected cell; andmeasuring a bit line current of the selected cell to obtain a thresholdvoltage of a MOS transistor in the selected cell, wherein the MOStransistor in the selected cell includes the first pass NMOS transistor,the second pass NMOS transistor, the first pull-down NMOS transistor,the second pull-down NMOS transistor, the first pull-up PMOS transistor,or the second pull-up transistor.
 2. The method according to claim 1,wherein measuring a threshold voltage of the first pass NMOS transistorincludes: initializing a gate electrode of the second pull-down NMOStransistor to be at a low level and a gate electrode of the firstpull-down NMOS transistor to be at a high level; after initializing,applying a supply voltage of the SRAM array to the first power line, thefirst substrate terminal, the first bit line, and the second bit line,applying a zero voltage to the second power line and the secondsubstrate terminal; sweeping a voltage of the word line from zero to thesupply voltage of the SRAM array by a pre-set step voltage; andmeasuring a current of the first bit line when sweeping the voltage. 3.The method according to claim 2, wherein the pre-set step voltage rangesfrom about 0.005 V to about 0.1 V.
 4. The method according to claim 2,wherein the supply voltage of the SRAM array ranges from about 0.5 V toabout 2.5 V.
 5. The method according to claim 2, wherein the controlvoltage ranges from about 1V to about 3V.
 6. The method according toclaim 1, wherein measuring a threshold voltage of the second pass NMOStransistor includes: initializing a gate electrode of the firstpull-down NMOS transistor to be at a low level and a gate electrode ofthe second pull-down NMOS transistor to be at a high level; afterinitializing, applying a supply voltage of the SRAM array to the firstpower line, the first substrate terminal, the first bit line, and thesecond bit line; applying a zero voltage to the second power line andthe second substrate terminal; sweeping a voltage of the word line fromzero to the supply voltage of the SRAM array by a pre-set step voltage;and measuring a current of the second bit line during the voltagesweeping.
 7. The method according to claim 1, wherein measuring athreshold voltage of the first pill-down NMOS transistor includes:applying a supply voltage of the SRAM array to the second power line andthe first substrate terminal, applying a zero voltage to the first bitline and the second substrate terminal; applying a control voltage tothe word line; sweeping voltages of the second bit line and the firstpower line from 0 V to the supply voltage of the SRAM array by a pre-setstep voltage; and measuring a drain current of the first bit line whilethe voltages of the second bit line and the first power line sweepingfrom 0 V to the supply voltage of the SRAM array.
 8. The methodaccording to claim 7, wherein the control voltage is higher than thesupply voltage of the SRAM array.
 9. The method according to claim 7,wherein the pre-set step voltage ranges from about 0.005 V to about 0.1V.
 10. The method according to claim 7, wherein the supply voltage ofthe SRAM array ranges from about 0.5 V to about 2.5 V.
 11. The methodaccording to claim 7, wherein the control voltage ranges from about 1Vto about 3V.
 12. The method according to claim 1, wherein measuring athreshold voltage of the second pull-down NMOS transistor includes:applying a supply voltage of the SRAM array to the second power line andthe first substrate terminal, applying a zero voltage to the second bitline and the second substrate terminal; applying a control voltage tothe word line; sweeping voltages of the first bit line and the firstpower line from 0 V to the supply voltage of the SRAM array by a pre-setstep voltage; and measuring a drain current of the first bit line, whilethe voltages of the first bit line and the first power line sweepingfrom 0 V to the supply voltage of the SRAM array.
 13. The methodaccording to claim 12, wherein the control voltage is higher than thesupply voltage of the SRAM array.
 14. The method according to claim 1,wherein measuring a threshold voltage of the first pull-up NMOStransistor includes: applying a supply voltage of the SRAM array to thefirst bit line and the first substrate terminal, applying a zero voltageto the first power line and the second substrate terminal; applying acontrol voltage to the word line; sweeping voltages of the second bitline and the second power line from the supply voltage of the SRAM arrayto zero voltage by a pre-set step voltage; and measuring a drain currentof the first bit line, while the voltages of the second bit line and thesecond power line sweeping from the supply voltage of the SRAM array tozero voltage.
 15. The method according to claim 1, wherein measuring athreshold voltage of the second pull-up NMOS transistor includes:applying a supply voltage of the SRAM array to the second bit line andthe first substrate terminal, applying a zero voltage to the first powerline and the second substrate terminal; applying a control voltage tothe word line; sweeping voltages of the first bit line and the secondpower line from the supply voltage of the SRAM array to zero voltage bya pre-set step voltage; and measuring a drain current of the second bitline, while the voltages of the first bit line, and the second powerline sweeping from the supply voltage of the SRAM array to zero voltage.16. The method according to claim 15, wherein the control voltage ishigher than the supply voltage of the SRAM array.
 17. The methodaccording to claim 15, wherein the pre-set step voltage ranges fromabout 0.005 V to about 0.1 V.
 18. The method according to claim 15,wherein the supply voltage of the SRAM array ranges from about 0.5 V toabout 2.5 V.
 19. The method according to claim 15, wherein the controlvoltage ranges from about 1V to about 3V.